Automated Pipelining in ASIC Synthesis Methodology: Gate Transfer Level
نویسندگان
چکیده
The paper presents Gate Transfer Level (GTL) as a general framework for synthesis of industrial complexity asynchronous quasi-delay-insensitive (QDI) circuits. The GTL flow automatically provides the finest degree of pipelining (gate-level) resulting in extremely high-performance designs. Automatic gate level pipelining is not possible for synchronous design due to the stage balance problem and clock related overheads (latches, clock skew and jitter). Experimental results show average 4.3x performance increase on MCNC benchmarks compared to synchronous RTL implementation.
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